1. Field of the Invention
The present invention relates to computing systems, and more particularly, to an elastic buffer module used in PCI Express devices.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®, or the extension of PCI known as PCI-X. More recently, PCI Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
Host systems are used in various network applications, including storage area networks (“SANs”). In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters, for example, host bus adapters (“HBAs”).
HBAs (a PCI Express device) that are placed in SANs receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing, as described above. HBAs operate as a transmitting device as well as the receiving device.
PCI Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI Express bus. PCI-Express uses discrete logical layers to process inbound and outbound information. In the PCI-Express terminology, a serial connection between two devices is referred to as a link.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
PCI Express, Fibre Channel and other serial interfaces use 8-bit to 10-bit encoding, in which each 8-bit character of source data is encoded into a 10-bit symbol prior to transmission. A receiving device to recover the original 8-bit character decodes the 10-bit data.
In order to recover data from a serial bit stream, the receiving PCI Express device performs clock recovery, de-serialization and symbol lock. In clock recovery, the receiving device generates a serial bit clock that is phase locked to the incoming serial bit stream. This is also known as bit synchronization. For de-serialization, the recovered clock is used to sample the incoming serial bit stream and convert it into parallel data. For symbol lock, the boundary between consecutive 10-bit symbols is determined and the de-serialized data is aligned to the boundary. After the symbol lock, the 10-bit data is sent to an Elastic Buffer module (may also be referred to as Elastic Buffer) and then the 10-bit data is decoded to 8-bit for further processing.
The Elastic Buffer, using a first-in-first-out memory space (for example, a circular buffer), typically receives symbols from a symbol lock module at the rate of one symbol/clock (for example, receive clock rate) and forwards symbols to other modules at another clock rate (for example, system clock rate). PCI Express allows the difference between clock rates to be up to 600 ppm. Clock rate compensation is used to control data flow from/to the elastic buffer.
The PCI Express standard allows a PCI Express device to insert or delete special symbols so that the elastic buffer does not overflow or under flow depending on the rate difference between the receive and system clocks. The underflow condition occurs when the system clock is faster than the receive clock, while the overflow condition occurs when the receive clock is faster than the system clock. One such symbol is the SKIP symbol (defined by the PCI Express standard) within a SKIP ordered set.
Typically, the elastic buffer uses the difference between a write and read pointer to determine the amount of information in the buffer. The write pointer indicates the location where the received data from the symbol lock module is written in the elastic buffer, while the read pointer indicates the storage location from where data is read from the elastic buffer. Once the difference is known, SKIP symbols may be inserted/deleted to avoid overflow/underflow conditions. However, the read and write pointers operate in different clock domains (system and receive clock domains) and hence the difference calculation itself may have errors. The deletion/insertion of SKIP symbols based on the erroneous calculation is not able to solve the underflow/overflow conditions when the data rate difference is operating at the theoretical limit. This theoretical limit is determined by the size of the Elastic Buffer and the maximum clock rate difference possible as specified in the PCI Express specification.
Therefore, there is a need for a method and system for efficiently managing underflow/overflow conditions in an elastic buffer.